(1) Field of the Invention
The invention relates to a method to reduce fluorine contamination on the surface of an integrated circuit device and, more particularly, to a method to remove fluorine using a high cathode temperature plasma treatment.
(2) Description of the Prior Art
The fabrication of integrated circuit devices typically involves a large number of steps to deposit and pattern various layers. In a typical sequence, a layer, or film, is deposited upon the wafer surface. A masking layer is then deposited over the film. The masking layer is patterned to reveal selected portions of the film while concealing other selected portions. The masking layer may then be used to mask an etching process that is used to selectively remove the exposed portion of the film. This type of sequence is common to semiconductor manufacturing but may result in undesirable consequences.
Referring now to FIG. 1, an exemplary prior art integrated circuit device structure is shown in cross section. A substrate 10 comprises, for example, a semiconductor such as silicon. An insulator layer 14 is formed overlying the substrate 10. A patterned metal layer 18 is formed overlying the insulator 14. A passivation layer 22 is formed overlying both the insulator layer 14 and the patterned metal 18. In this particular example, the metal section 18 is patterned to form a bonding pad for the circuit. It is necessary, therefore, to form openings, or pad openings, in the passivation layer 22 to thereby expose the metal pad 18.
To form the openings, a masking layer 24 is deposited overlying the passivation layer 22. For example, a photoresist layer 24 is coated overlying the passivation layer 22. This deposited photoresist layer 24 is first exposed to actinic light through a mask and is then developed to remove portions overlying the metal bonding pad 18 as shown. The patterned masking layer 24 is then used as a mask for etching the pad openings in the passivation layer 22.
Typically, the etching process for the pad etch comprises a fluorine-containing chemistry. For example, CF4 or SF6 may be used in the dry pad etch process. In these processes, the fluorine ions 28 exhibit excellent etching properties in terms of selectivity and anisotropic etching as shown in FIG. 2.
A problem with the fluorine-based chemistry is also demonstrated in FIG. 2. A high concentration of ionic fluorine species 28 is left behind after the etch. The presence of this fluorine contamination causes several problems. First, since the metal layer 18 is typically aluminum or an alloy of aluminum and copper, the fluorine tends to cause corrosion. Second, the fluorine causes pad crystal defects. These problems ultimately lead to poor bonding capability. This is especially true if a long queue (Q) time occurs between the pad etching process and any subsequent pad alloy processing. The presence of the fluorine, coupled with a long waiting time (sometimes many weeks) and environmental conditions (such as humidity) can cause excessive corrosion and crystal defects as shown by Auger data.
Several prior art inventions describe pad etching and contamination removal methods. U.S. Pat. No. 6,162,733 to Obeng teaches a method to remove alkali metal and halogen-based contaminants from an integrated circuit device. Halogen-based contaminants are removed using a plasma process. U.S. Pat. No. 6,063,207 to Yu et al discloses etching a bonding pad opening using a fluorine based plasma. Fluorine contamination is then removed using a rinse with a DI water solution containing CO2. U.S. Pat. No. 5,824,234 to Jou et al describes a bonding pad method. After etching the bonding pad opening with a fluorine-containing plasma, the fluorine contamination is removed by dipping the wafer in a TMAH solution. U.S. Pat. No. 5,380,401 to Jones et al teaches a method to remove fluorine contamination from bonding pads. A plasma process using CO2 and Ar is described. U.S. Pat. No. 5,970,376 to Chen discloses a method to remove a fluorocarbon polymer from a wafer surface using an inert gas plasma. The focus is treating a spin-on material. U.S. Pat. 5,770,098 to Araki et al describes a plasma etching process. U.S. Pat. No. 5,942,446 to Chen et al discloses a method of patterning a silicon-containing layer using plasma etching. U.S. Pat. No. 5,776,832 to Hsieh et al teaches a method to prevent corrosion of metal lines by performing an O2 ashing step after etching metal lines with BCl3 or with Cl2. U.S. Pat. No. 5,755,891 to Lo et al discloses a method to treat after metal etch. The method uses a plasma comprising a mixture of O2 and CF4 gases. U.S. Pat. No. 6,136,680 to Lai et al describes methods to process fluorinated silicate glass (FSG) film by performing plasma treatments using N2, NH3, O2, or N2O or by performing Ar sputtering. U.S. Pat. No. 5,854,134 to Lan et al teaches performing a plasma treatment on a metal layer using a fluorine containing plasma to thereby form a thin polymeric passivation layer on the metal. U.S. Pat. No. 5,731,243 to Peng et al discloses a method to remove residue from a bonding pad using a dip in a solution comprising DMDO and MEA followed by an oxygen plasma treatment.